Adaptive variable-gain phase and frequency locked loop for rapid carrier acquisition

ABSTRACT

An apparatus and method for improving the performance of a satellite communications modem is disclosed. The invention is particularly applicable to mobile satellite receivers, and includes a variable-gain automatic frequency controlled (AFC) loop, the gain of which is controlled adaptively, based on the AFC lock status and the lock status of the modem&#39;s inner loop, in addition to other parameters determined by the invention.

INCORPORATION BY REFERENCE

The following materials are incorporated by reference herein: ImprovingFrequency Acquisition of a Costas Loop by Charles R. Cahn, IEEETransactions on Communications, Vol. Com-25, No. 12, December 1977;Analysis of Lock Detection in Costas Loops by A. Mileant and S. Hinedi,Technical Support Package for NASA Techbrief, Vol. 15, No. 7, Item No.86, July 1991, JPL Invention Report, NP0-18102/7612.

BACKGROUND OF THE INVENTION

a. Field of the Invention

The present invention relates to satellite communication systems thatuse phase shift keyed (PSK) or differential phase shift keyed (DPSK)signalling. In particular, it relates to mobile satellite communicationsreceivers which use PSK or DPSK signalling.

b. Problems in the Art

Many modulation schemes, e.g., PSK, DPSK, frequency shift key (FSK),single side band (SSB)-analog, and amplitude modulation (AM)-analog,require an accurate estimate of the system's carrier frequency forproper demodulation of the received signal. Demodulation of PSK and DPSKsignals is particularly susceptible to a receiver's tuned frequencybeing offset from the desired carrier frequency. In addition to thecarrier frequency, coherent-demodulation also requires estimation of thecarrier phase. Generally, a Costas or squaring loop (which are morecomplex forms of the basic phase locked loop) provides the requiredestimate of carrier frequency and phase for coherent demodulation of PSKor DPSK signals. Unfortunately, Costas and squaring loops have only alimited capture range. To provide adequate loop demodulationperformance, especially in low signal to noise ratio applications, thecapture ranges of Costas and squaring loops must be limited. This isbecause the phase noise in the loop is proportional to the loopbandwidth which also governs the capture range. Consequently, Costas andsquaring loops' capture ranges are often aided by supplemental means.One such means is spectral analysis of the received signal.

Spectral analysis of a mobile satellite system's received signal issometimes employed to aid a loop in carrier acquisition. Spectralanalyses are performed and averaged, yielding a coarse estimate of thereceiver's frequency offset from the carrier. Although this approachwill typically provide a frequency estimate within the loop's capturerange, this approach requires a great deal of processing power.Applications involving low signal to noise ratio require even moreprocessing because the desired signal is masked by noise and must beextracted using several Fast Fourier Transforms (FFTs) followed byaveraging and some form of feature extraction. Processing powerrequirements severely limit the applicability of this approach to aidingloop acquisition.

Another approach to aiding phase locked loop (or PLL) acquisitionemploys a frequency locked loop to initially provide the primarycorrection and drive to the phase locked loop's VCO, when the offsetbetween the frequency of the desired signal and that of the VCO isrelatively large, and using the PLL's inherent capture ability when theoffset is small.

In its most basic configuration, a Costas loop's capture range iscomparable (about 1.5 times greater) to its single-sided loop noisebandwidth. One can extend the capture range of the basic loopconsiderably beyond the loop noise bandwidth by creating a component inthe VCO's input drive that was proportional to the instantaneousfrequency offset between the VCO's output and the input signal. Addingan automatic frequency control (AFC) loop around the Costas loopprovides the desired VCO drive signal.

Although the addition of an AFC loop around the Costas loop increasesthe composite loop's capture range, the acquisition time of thecomposite loop is long because the AFC loop bandwidth has to be smallrelative to that of the Costas loop. This is so that the AFC loop'scontribution to the VCO phase noise is small. In fact, in Cahn's work(referenced above and incorporated by reference herein), the AFC loopbandwidth is limited to 1/10 of the Costas loop bandwidth, at most. Forslowly varying signals, in applications where channel utilization is notextremely critical, this bandwidth penalty is tolerable and, many times,the increase in capture range more than compensates for the sacrifice inloop bandwidth. However, for many applications, loop bandwidth iscritical and this approach is untenable.

In particular, mobile satellite communication systems operate with lowsignal to noise ratios. Furthermore, the mobile satellite receivertypically "hops" its tuned frequency over a range of uncertainty untilit locates its desired carrier frequency. This "hopping" effectivelycreates a step-function input to the carrier acquisition subsystem. Alimited loop bandwidth constricts an acquisition system's response to arapidly changing input like a step-function.

Satellite time is extremely expensive, and anything that reduces asatellite communication system's acquisition time enhances theutilization of a valuable resource. A technique for improving channelutilization through the reduction of acquisition time greatly improvesthe carrier acquisition system's value. Achieving this improvement isespecially difficult when faced with the obstacles presented by a stepfunction input in combination with a limited loop bandwidth.

It is therefore an object of the present invention to provide means anda method for minimizing the search time required for a satellitecommunication acquisition system to acquire an associated communicationchannel.

It is also an object of the present invention to minimize the timerequired for a mobile satellite receiver to reacquire a satellite signalafter interruption. Such systems require narrow tracking bandwidths inorder to provide good demodulation performance at low signal-to-noiseratios. Fading and blocking of signals cause mobile satellite systems tosuffer much more frequently from the loss of carrier than stationarysatellite systems. Rapid reacquisition is therefore especially importantto mobile satellite systems.

It is a further object of the present invention to provide means and amethod for acquisition and tracking of a satellite communication signalwhich is cost effective.

Some carrier acquisition subsystems use a computation intensive approachto expand the capture range of a phase locked loop. In these systems,high speed, relative costly processors continuously run Fast FourierTransforms in the background. It is therefore a further object of thesystem of the present invention to eliminate the expense associated withhigh performance processing components by obviating the need forcontinuous Fast Fourier Transform computation.

It is a further object of the present invention to provide means and amethod for extending the capture range of a PLL (phase locked loop), sothat it can pull in signals with large frequency offsets, withoutdegrading the signal to noise ratio in the tracking mode.

Other objects, features, and advantages of the invention will becomeapparent with reference to the accompanying specification and claims.

SUMMARY OF THE INVENTION

The present invention is an adaptive, variable AFC gain, phase lockedloop, which aids both basic PLLs or PLLs extended to Costas or squaringloops by providing both a wide capture bandwidth during the PLL'sinitial acquisition and narrow loop noise bandwidth while the loop istracking. In an embodiment where the PLL has been extended to a Costasor squaring loop, the resulting AFC aided PLL is suitable fordemodulating mobile satellite PSK signals.

The system of the present invention sets the AFC loop gain to maximumduring initial acquisition, to a medium level when the PLL is out oflock but nevertheless in the tracking mode, and to a minimum value whenthe PLL is locked or when the carrier synchronizer is in a waiting mode.

The system of the present invention estimates how far the loop'stransient response is from its equilibrium point, provides a reliableAFC lock detection method and means, and discriminates between initialacquisition and tracking modes. Based on these results, the system ofthe present invention sets the AFC loop gain so as to minimize capturetime (maximize capture bandwidth) and yet maintains the incomingsignal's signal to noise ratio during tracking (by providing a narrowloop noise bandwidth). It is important to note that the system of thepresent invention bases AFC gain control, not on PLL lock, but on itsown estimate, derived from transient response analysis of proximity ofthe VCO frequency to the input frequency. This estimate is at least oneorder of magnitude more rapid than one based on PLL lock alone.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an AFC-aided Costas loop described by Cahn.

FIG. 2 is a detailed diagram of the frequency discriminator of FIG. 1.

FIG. 3 is a block diagram of the preferred embodiment of the system ofthe present invention showing the adaptive AFC gain control.

FIG. 4(a)-(b) illustrates the motivation for an AFC lock detection inputto the adaptive AFC loop gain control mechanism of the presentinvention.

FIG. 5 is a flowchart for the gain switching decisions for the system ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

To assist in a better understanding of the present invention, a specificembodiment of the invention will now be set forth in detail. Thisdescription is not inclusive of all forms the invention may take, but isillustrative only.

Reference characters used throughout this description including numbers,letters and combinations of the same, refer to the appended drawings andare used to indicate specific parts or locations in the drawings. Thesame reference characters will be used for the same parts and locationsthroughout all the drawings unless otherwise indicated.

FIG. 1 is a block diagram of an AFC frequency discriminator-aided Costasloop. The input to the Costas loop is a complex base band signalconsisting of inphase and quadrature components obtained by frequencytranslating the received bandpass intermediate frequency signal to acenter frequency of 0 HZ. The input to the Costas loop can be writtenas:

    (X)=m(t).exp{j(wt+a)}

where t is the time variable, m(t) is the real amplitude of the complexbaseband input, w is the angular frequency in radians per second, and ais the phase offset relative to an arbitrary reference at the receiver.Because a nonfading channel is assumed for this discussion, "a" and "w"are represented as time invariant parameters.

To illustrate phase acquisition in a Costas loop, we first assume thatfrequency acquisition has been achieved, but that phase acquisition hasnot--that is, the VCO 18 output frequency (E) equals w but its phase isnot equal to a. The VCO output is given by (E)=exp{j(wt+a')}.

Multiplier 2, multiplies the input signal, (X), by the complex conjugateof VCO 18 output (E). Resulting signal (A) equals m(t) exp(jb) where bis the phase error between VCO 18, output (E) and input (X): ##EQU1##Lowpass filter 4 filters the complex error signal (A) to obtain areduced noise version (B) equal to m'(t)exp{jb}. The filter delay isassumed to be negligibly small, and therefore the phase error b isunchanged. (B) is then split into its real, m'(t) cos(b) 6, andimaginary m'(t) sin(b) 8, components. Hard limiter 10, produces a "1"output for one phase of the BPSK channel signal and a "-1" output forthe other phase. Multiplier 12 then multiples m'(t) sin(b) times thehard limiter 10 output resulting in a signal e(t)=|m'(t)|.sin(b), whichis the feedback loop error signal. The output of lowpass filter 14, thefiltered error signal, is the Costas loop contribution to control of theVCO 18. The bandwidth of lowpass filter 14 is much less than that oflowpass filter 4. Lowpass filter 14 therefore almost completelydetermines the frequency and time response of the Costas loop.

The capture range of the Costas loop 24, just described, is typicallyslightly greater than the loop noise bandwidth. A frequency locked loopcomposed of frequency discriminator 20, and AFC loop filter 22, areadded to the basic Costas loop to significantly expand the capture rangeof the Costas loop. Frequency discriminator 20 generates an output whichis proportional to the frequency of the input signal; and AFC loopfilter 22 averages modulation-induced phase transitions in the frequencydiscriminator 20 output to a mean value close to zero. The output of AFCloop filter 22, therefore, is proportional to the instantaneousfrequency of the input signal, with the self noise caused bymodulation-induced phase transitions reduced. The outputs of the AFCloop filter 22 and the Costas loop filter 14 are combined in adder 16 toform the composite VCO input e'. The VCO output frequency (in radians)is given by w=k.e', k being a fixed loop gain factor.

FIG. 2 depicts frequency discriminator 20 in more detail. In operation,multiplier 26 multiplies the complex conjugate of its input exp{jwt+φ}by a version of the input signal delayed by τ, that is exp{j(w(t+τ)+φ)},yielding exp{jwτ}. Module 28 takes the imaginary part of this resultingsignal to obtain sin(wτ). For small values of the argument, sin(wτ) isproportional to w. Thus, discriminator 20, produces an outputproportional to the input frequency w. The primary function of thediscriminator is to provide an output that generates a correctionalforce of one sign for positive frequency offsets and of the oppositesign for negative frequency offsets.

Adding the AFC loop to the Costas loop improves the capture range;however, the AFC loop bandwidth is limited to at most 1/10 the Costasloop bandwidth. If the AFC loop bandwidth is greater than 1/10 theCostas loop bandwidth, the AFC loop will contribute significantly to theVCO phase noise during tracking. This limitation on the AFC loopbandwidth is a significant drawback in applications where rapid carrieracquisition is required, such as when the receiver's local oscillator isvaried over a range of frequency uncertainty to search for the desiredsignal. Satellite communication systems often employ this frequencysearch technique at the receiver, and the limited channel capacity ofsatellite communication systems places a premium on maximum utilizationof available capacity. In order to achieve maximum utilization, thePLL-based receiver must acquire the satellite carrier as rapidly aspossible. The bandwidth limitation imposed on the AFC loop in order tolimit the phase noise power of the composite loop frustrates the goal ofrapid acquisition.

The present invention compensates for the shortcomings of the prior artAFC-aided PLL design by employing a variable gain AFC. By setting theAFC gain high, the bandwidth of the composite PLL is greatly expanded,thereby maximizing channel usage. During other periods of operation,lower AFC gains are applied to minimize the AFC loop's contribution tothe composite loop noise.

FIG. 3 is a simplified block diagram of the preferred embodiment of thepresent invention. The elements, in addition to the prior AFC aidedloop, include sample rate reduction module 26, lowpass filter 28, AFClock detector 30, AFC gain multiplier 32, Costas loop lock detector 34,gain algorithm processor 36, and waiting time counters 38.

The addition of these elements provides the PLL with fast initialcarrier acquisition, low phase noise during carrier tracking, fastcarrier reacquisition after signal fading and blockages, and the abilityto track time-varying Doppler shifts. A variety of measurements aredeveloped and used by the above additional elements to control the AFCloop gain, thereby controlling bandwidth and noise in an optimal mannerduring the various states of PLL operation.

The two major modes of operation for the PLL of the present embodimentare, one, initial acquisition, and, two, tracking. The initialacquisition mode starts when a receiver tunes to a new channel and endswhen the PLL first achieves lock. The tracking mode commences when thePLL first achieves lock. If the PLL is out of lock for a specifiedperiod (25 seconds in the present embodiment), the gain switchingalgorithm returns the PLL to the initial acquisition mode.

The flowchart of FIG. 5 illustrates the decision-making process of thegain switching algorithm and provides an overview of the operation ofthe present invention. After initialization, the processor running thealgorithm determines whether the PLL is in the initial acquisition mode,decision block 40. The system is in the initial acquisition mode if theCostas loop has never acquired lock since the receiver tuned to thecurrent frequency. The system reenters the initial acquisition mode ifthe Costas loop is continuously out of lock for 25 seconds. If the PLLis not in the initial acquisition mode, then it is in the tracking mode.After determining that the PLL is in the tracking mode, the PLL ischecked in block 42 to determine whether it is locked. If the PLL islocked, then the minimum AFC gain is applied in block 44. If the PLL isnot locked, however, then the medium gain is applied in block 46. Theexpectation here is that a temporary interruption has occurred in thesignal reception and it is therefore not necessary to use the maximumAFC loop gain. However, the 25 second counter is started as soon as aloss of PLL lock is detected, and is reset when PLL lock returns. If the25 second counter runs its full length, "initial acquisition" mode isdeclared, as mentioned above.

If it is determined at decision block 40, that the PLL is in the initialacquisition mode, the AFC loop is checked for lock. If the AFC loop isnot locked, maximum gain is applied to the AFC loop in block 50. If theAFC loop is locked, the minimum gain is applied in block 52, and theprocessor waits a specified period (0.8 seconds in the presentembodiment), during which the PLL is continuously checked for lock, asshown in block 56. If, at the end of the waiting period the PLL is notlocked, maximum gain is applied in block 58, after which the processorexits the adaptive gain control module. If at block 56, the PLL isdetermined to be in lock, the minimum gain 60, is applied.

The AFC loop of the present invention uses a nonzero minimum gain in thetracking mode, thereby allowing a demodulator, for example, to trackslow frequency drifts in the transmitter and receiver frequencyreferences. The PLL rapidly resynchronizes after temporary loss of lockbecause the processor applies medium gain in this case. Since temporaryloss of lock is most often due to fading or blocking of the signal, thefrequency will not change significantly with a temporary loss of lock.Therefore, a medium gain level for the AFC loop is appropriate duringtemporary losses of lock.

The waiting period of block 54, and the initial acquisition timing ofblock 40, are implemented by counters 38 of FIG. 3. Costas loop lockdetect 34 provides lock detection for decision blocks 56 and 42 of FIG.5. The gain adjustments of blocks 44, 46, 50, 52, 58, and 60 areimplemented by AFC gain multiplier 32 of FIG. 3. Costas loop lockdetect, 34, is a standard lock detect implementation. (See, for example,the Mileant and Hinedi article incorporated by reference herein.) TheAFC lock detect block 30, basically monitors the time derivative of thefiltered AFC-loop error signal to determine when there is a change inits direction (increasing or decreasing). The direction is given by thefirst derivative of the filtered AFC error signal, and a change indirection is indicated by the product of two successive firstderivatives being negative. In the digital signal processing (DSP)implementation used in the preferred embodiment, derivatives areimplemented as finite differences.

The sign change in the derivative of this signal provides an indicationof the AFC loop's proximity to lock. This is a characteristic of thestep response of any finite-bandwidth linear system, as illustrated inFIGS. 4A and 4B. This information is used, as explained above, by theAFC loop gain algorithm to set the proper gain at AFC gain multiplier32.

FIGS. 4A and 4B illustrate the AFC loop lock detection process of thepreferred embodiment of the present invention. The lock detector outputis used, as explained above, to decide when to modify the AFC gain. Agraphical representation of the AFC lock detection process is given inFIGS. 4A and 4B, which plot the filtered AFC error voltage (output offilter 28) as a function of time.

In operation, the gradient (time derivative) of the AFC error voltage ismonitored for a change in sign. As shown in FIG. 4A, the output of 28 issampled at three equally spaced instants to yield samples V₁, V₂, andV₃. When the transient response changes direction (i.e., gradientchanges sign), the sign of V₃ -V₂ is different from the sign of V₂ -V₁.Therefore, whenever (V₃ -V₂)×(V₂ -V₁) is less than 0, the gradient haschanged sign. This change in sign, as is apparent from FIG. 4A, ischaracteristic of the AFC error voltage waveform when the AFC nearslock.

There is, as illustrated in FIG. 4B, a chance that noise may induce a"false lock" indication on the part of the AFC lock detector. Tomitigate the hazard of a false lock reading, the following threemeasures are taken.

First, the AFC error signal is lowpass filtered in block 28 in FIG. 3,before feeding it to the gradient determination module. The bandwidth ofthis filter is made as low as possible, limited by the required responsetime of the adaptive gain control system.

Second, the sample rate is decimated, in block 26, FIG. 3, therebyspacing the samples far enough apart that the likelihood of anoise-induced gradient sign reversal is reduced. For the preferredembodiment, the decimation factor was 100. Additionally, by reducing thesample rate in 26, before filtering in block 28, the implementation oflowpass filter 28, is simplified.

Finally, in low SNR conditions, spurious locks may occasionally occur inspite of the above measures. If after waiting for a predetermined time(0.8s in the preferred embodiment) after AFC lock, the PLL is notlocked, then the system of the present invention determines that the AFClock was false and returns the AFC gain level to that prior to the AFClock detection. The waiting period is set long enough to allow the PLLto acquire a carrier from the edge of its capture range.

It will be appreciated that the present invention can take many formsand embodiments. The true essence and spirit of this invention aredefined in the appended claims, and it is not intended that theembodiment of the invention herein set forth should limit the scopethereof.

For example, other implementations of the general principles of thepresent invention employed by the preferred embodiment set forth hereinare possible. The AFC gain could be continuously variable, rather thandiscreet as set forth in the preferred embodiment. In such a embodiment,the AFC gain would be proportional to the gradient of the AFC errorsignal.

Although the present embodiment is based on DSP software, a hardwareembodiment is also feasible and is especially attractive in high speedapplications. Referring to FIG. 3, for example, multipliers 2, 12, and32 could be four-quadrant analog multipliers; filters 28, 22, 4, and 14could be analog filters; sampling means 26 could be placed after filter28 and take the form of an A/D converter; and the AFC lock detect 30,and AFC gain algorithm 36, could be performed either in discreet digitalhardware, a programmable logic device, or a microprocessor. In that casea D/A converter would be required between the AFC gain algorithm 36, andthe AFC gain module 32, to convert the digital AFC gain value to ananalog value. The PLL lock detect function could be a fully analogmodule whose output, fed to the AFC gain algorithm 36, is an on/offlogic value.

Further, the system could be implemented in various custom, semi-customor field programmable integrated circuits including gate arrays,programmable logic devices, etc. which may or may not incorporate bothanalog an digital functions within the same integrated circuit.

What is claimed is:
 1. In a radio communication receiver, a carrierphase and frequency synchronizer that extends the capture range of aphase-locked-loop which is integral to the synchronizer, whilemaintaining low noise bandwidth of the synchronizer, comprising:a phaselocked loop generating a first error signal and having an oscillatorcontrolled by a composite third error signal; an automatic frequencycontrol loop producing a second error signal; means for combining thefirst error signal of said phase locked loop with the second errorsignal of said automatic frequency control loop and delivering thecomposite third error signal to the phase locked loop's oscillator;means for controlling the gain of the automatic frequency control loop;means for determining whether said phase locked loop is locked; saidmeans for determining having an output directed to said means forcontrolling the gain of said automatic frequency control loop; means,independent of the said means for determining phase locked loop lock,for determining whether said automatic frequency control loop is lockedand having an output directed to said means for controlling the gain ofsaid automatic frequency control loop; means for decimating theautomatic frequency control loop error signal; and, means for filteringthe decimated automatic frequency control loop error signal and havingan output directed to said means for controlling the gain of saidautomatic frequency control loop.
 2. The synchronizer of claim 1 whereinsaid phase-locked-loop is one of Costas or squaring phase locked loops.3. The synchronizer of claim 1 wherein said automatic frequency controlloop includes means for determining changes in the sign of the filtereddecimated automatic frequency control error signal when said automaticfrequency control loop is locked.
 4. The synchronizer of claim 1 whereinsaid means for controlling the gain of the automatic frequency controlloop comprises a microprocessor-based circuit.
 5. The synchronizer ofclaim 1, wherein said means for controlling the gain of the automaticfrequency control loop comprises a combination of analog and digitalcircuitry.
 6. The synchronizer of claim 1 wherein said means forcontrolling the gain of the automatic frequency control loop comprisesan application-specific integrated circuit.
 7. In a radio communicationreceiver having a carrier synchronizer having a phase locked loop and anautomatic frequency control loop; a method for carrier phase andfrequency synchronization that extends the capture range of the carriersynchronizer, while maintaining the overall bandwidth of saidsynchronizer and preserving the input signal's signal to noise ratio,comprising:determining when said automatic frequency control loop islocked; determining when said phase locked loop is locked; determiningwhether said synchronizer is in an initial acquisition or tracking mode;and controlling the gain of said automatic frequency control loop basedon whether said automatic frequency control loop is locked, whether saidphase locked loop is locked, and whether said synchronizer is in aninitial acquisition or tracking mode.
 8. The method for carrier phaseand frequency synchronization according to claim 7, furthercomprising:generating an automatic frequency control error voltage;decimating said automatic frequency control error voltage; filtering thedecimated automatic frequency control error voltage; determining theslope of the filtered, decimated automatic frequency control errorvoltage; making an initial determination that the automatic frequencycontrol is locked when the slope of the decimated, filtered automaticfrequency control error voltage changes sign; and making a finaldetermination that both said phase and frequency are synchronized whenafter waiting a predetermined period of time following said initialdetermination, said phase locked loop is determined to be locked.
 9. Themethod for carrier phase and frequency synchronization according toclaim 7 further comprising controlling the gain of said phase lockedloop wherein the gain can take on a continuum of values.
 10. The methodfor carrier phase and frequency synchronization according to claim 7further comprising controlling the gain of said phase locked loopwherein the gain can take on discrete values.
 11. The method for carrierphase and frequency synchronization according to claim 7 furthercomprising controlling the gain of said phase locked loop wherein thegain takes on a low but nonzero value during the tracking mode.
 12. Themethod for carrier phase and frequency synchronization according toclaim 7 further comprising controlling the gain of said phase lockedloop wherein the gain takes on a high value during initial acquisition,a medium value when said phase locked loop is out of lock butnevertheless in the tracking mode, and a minimum gain when said phaselocked loop is locked or when the carrier synchronizer is in the waitingmode.
 13. In a radio communications receiver's carrier phase andfrequency synchronizer, means for extending capture range of thesynchronizer comprising:a phase locked loop; an automatic frequencycontrol loop coupled to the phase locked loop through a common voltagecontrolled oscillator, fed by summed error signals of the phase lockloop and the automatic frequency control loop; and means forautomatically switching automatic frequency control gain among variousvalues.
 14. A radio communication receiver wherein a carrier phase andfrequency synchronizer incorporates a first feedback loop structurehaving an input signal, the synchronizer comprising:means forautonomously producing an estimate of a current operating point of saidfeedback loop structure relative to transient response of said firstfeedback loop structure and generating an estimate; and, means forverifying whether the estimate of the current operating point is true orfalse, based on a status of an independent indicator of the currentoperating point, where said independent indicator is independent of allparameters calculated in said first feedback loop.
 15. The receiver ofclaim 14 wherein the means for autonomously estimating estimates thecurrent feedback loop operating point by utilizing a gradient of anerror signal produced in said feed back loop structure to determineproximity to an equilibrium value of the error signal.
 16. The receiverof claim 14 wherein the means for verifying utilizes a predeterminedwaiting period, during which a status of the independent indicator ismonitored.
 17. The receiver of claim 14 wherein the independentindicator of the current operating point is a lock detector of a secondfeedback loop, operating with the same input signal as the firstfeedback loop.